I'm currently a Research Scientist at Uber ATG Toronto. I completed my MSc in Computer Science (Machine Learning Group) at the University of Toronto (2016-2018) and was supervised by Raquel Urtasun. Prior to that I completed my BASc in Mechanical Engineering (Mechatronics Program) at the University of British Columbia (2011-2016). My research interests lie on the intersection of Computer Vision and Machine Learning. My CV is available here.
My e-mail is justin dot j dot w dot liang at gmail dot com.
Convolutional Recurrent Network for Road Boundary Extraction
Justin Liang*, Namdar Homayounfar*, Wei-Chiu Ma, Shenlong Wang, Raquel Urtasun. (CVPR 2019)
End-to-End Deep Structured Models for Drawing Crosswalks
Justin Liang, Raquel Urtasun. (ECCV 2018)
TorontoCity: Seeing the World with a Million Eyes
Shenlong Wang, Min Bai, Gellert Mattyus, Hang Chu, Wenjie Luo, Bin Yang, Justin Liang, Joel Cheverie, Sanja Fidler, Raquel Urtasun. (ICCV 2017, Spotlight)
CSC2541: Topics in Machine Learning - Sport Analytics (Winter 2017)
Gave a lecture on two activity recognition papers: End-to-end Learning of Action Detection from Frame Glimpses in Videos and Detecting Events and Key Actors in Multi-Person Videos.
Unsupervised Learning of Basketball Offensive Plays
Implemented a combination of a CNN and LSTM to generate offensive basketball plays given the basketball and defensive basketball player trajectories.
Detection and Tracking of Basketball Players
Performed detection and tracking of basketball players using Faster-RCNN and Deep SORT.
Egg Yolk Consistency Measurement Device
Designed and developed a device that measures the yolk consistancy of an egg by oscillating it on a spring. Please refer to my partner in crime who has written a nice webpage about this here.
Elevator Simulation [CODE]
Simulated an elevator system using principles of concurrent systems such as data pools, pipelines and semaphores in C++.
Motor Control Using a MSP430
Designed a proportional controller and used it to control a DC motor with a MSP430 microcontroller. This was done by taking in encoder data and adjusting the timer to produce the correct PWM duty cycle.
8 Bit CPU
Built a simple CPU in VHDL consisting of an ALU and a register file on the Altera Cyclone II FPGA.